Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, fabrication of fine features in the semiconductor ICs presents difficulties. One particular difficulty is presented by electrical interconnect formation through dielectric layers to connect to source and drain regions of the FETs. Conventional techniques that are employed to form the electrical interconnects often compromise the gate electrode structure. For example, a nitride cap may be formed over the gate electrode structure prior to via etching through the dielectric layers with the electrical interconnects formed in the vias. However, both oxide and nitride dielectric layers generally overly the source and drain regions, and the vias must be etched through both the oxide and nitride dielectric layers to properly connect the source and drain regions to the electrical interconnect. Because the nitride cap is susceptible to nitride etch, and because conventional oxide etchants also generally etch nitrides (albeit at a significantly lesser rate than oxides), the nitride cap is prone to etch-through especially when a ratio of dielectric layer thickness to nitride cap thickness is high. As a result, the gate electrode structure underlying the nitride cap may be compromised, resulting in device reliability concerns. While steps may be taken to protect the nitride cap during etching of the vias to form the electrical interconnects, any added layers over the dielectric layer and nitride cap must still be etched during via formation such that nitride cap etch-through may still be a concern. Further, the additional of further layers over the nitride cap may impact performance of the FETs.
Accordingly, it is desirable to provide integrated circuits and methods of forming integrated circuits with adequate protection of the gate electrode structure while enabling the electrical interconnects to be properly formed. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.